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| 1 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 32m/64m/128m [x8/x16] single 3v page mode flash memory advanced information features ? 2.7v to 3.6v operation voltage ? block structure - 32 x 128kbyte erase blocks (32m) - 64 x 128kbyte erase blocks (64m) - 128 x 128kbyte erase blocks (128m) ? fast random / page mode access time - 120/25 ns read access time (32m) - 120/25 ns read access time (64m) - 150/25 ns read access time (128m) ? 128-bit protection register - 64-bit unique device identifier - 64-bit user programmable otp cells ? 32-byte write buffer - 6 us/byte effective programming time ? enhanced data protection features absolute protec- tion with vpen = gnd - flexible block locking - block erase/program lockout during power transi- tions performance ? low power dissipation - typical 15ma active current for page mode read - 80ua/(max.) standby current - deep power-down current: 5ua ? high performance - block erase time: 2s typ. - byte programming time: 210us typ. - block programming time: 0.8s typ. (using write to buffer command) ? program/erase endurance cycles: five grades-- "c1" stands for 10 cycles "c2" stands for 100 cycles "c3" stands for 1,000 cycles "c4" stands for 10,000 cycles "c5" stands for 100,000 cycles (please refer to ordering information of page 47) software feature ? support common flash interface (cfi) - flash device parameters stored on the device and provide the host system to access. ? automation suspend options - block erase suspend to read - block erase suspend to program - program suspend to read hardware feature(not for 48-tsop/48-rtsop) ? a0 pin - select low byte address when device is in byte mode. not used in word mode. ? sts pin - indicates the status of the internal state machine. ? vpen pin - for erase /program/ block lock enable. ? vccq pin - the output buffer power supply, control the device 's output voltage. packaging - 48-lead tsop (for mx28f128j3) - 48-lead rtsop (for mx28f128j3) - 56-lead tsop - 48-ball flip chip csp (for MX28F320J3/640j3) - 64-ball csp technology - mx28f128j3 using nbit (0.25u) flash technology - MX28F320J3/640j3 using nbit (0.35u) flash tech- nology
2 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 general description the mxic's MX28F320J3/640j3/128j3 series flash use the most advance 2 bits/cell nbit technology, double the storage capacity of memory cell. the device provide the high density flash memory solution with reliable perfor- mance and most cost-effective. the device organized as by 8 bits or by 16 bits of output bus. the device is packaged in 48-lead tsop, 48-lead rtsop, 56-lead tsop, 48-ball flip chip csp and 64- ball csp. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the device offers fast access time and allowing opera- tion of high-speed microprocessors without wait states. to eliminate bus contention, the device has separate chip enable (ce0, ce1, ce2) and output enable (oe) con- trols. the device augment eprom functionality with in- circuit electrical erasure and programming. the device uses a command register to manage this functionality. the mxic's nbit technology reliably stores memory con- tents even after the specific erase and program cycles. the mxic cell is designed to optimize the erase and program mechanisms by utilizing the dielectric's charac- ter to trap or release charges from ono layer. the device uses a 2.7v to 3.6v vcc supply to perform the high reliability erase and auto program/erase algo- rithms. the highest degree of latch-up protection is achieved 3 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 pin configuration 48-tsop (12mm x 20mm) (for mx28f128j3 word mode only) 48-rtsop (12mm x 20mm) (for mx28f128j3 word mode only) we a17 a16 a15 a14 a13 a12 a11 a10 a9 a20 a22 a21 a19 a18 a8 a7 a6 a5 a4 a3 a2 a1 ce0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 gnd gnd q15 q7 q14 q6 q13 q5 q12 q4 vcc vcc a23 q11 q3 q10 q2 q9 q1 q8 q0 oe gnd reset(*) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx28f128j3 (x16 only) normal type (* reset pin : high enable) we a17 a16 a15 a14 a13 a12 a11 a10 a9 a20 a22 a21 a19 a18 a8 a7 a6 a5 a4 a3 a2 a1 ce0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 gnd gnd q15 q7 q14 q6 q13 q5 q12 q4 vcc vcc a23 q11 q3 q10 q2 q9 q1 q8 q0 oe gnd reset(*) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx28f128j3 (x16 only) reverse type (* reset pin : high enable) 4 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 48 flip chip csp (for MX28F320J3/640j3) a14 a b c d e f 1 2345 6 78 a15 a16 a17 vccq gnd a12 a11 a13 q14 q15 q7 a9 we a10 q5 q6 q13 vpen reset a22 q11 q12 q4 8mm vcc a19 a21 q2 q3 vcc a20 a8 a18 a7 q8 q9 q10 a6 a4 ceo q0 q1 a5 a3 a2 13 mm a1 gnd oe 56 tsop (14mm x 20mm) a22 ce1 a21 a20 a19 a18 a17 a16 vcc a15 a14 a13 a12 ce0 vpen reset a11 a10 a9 a8 gnd a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nc we oe sts q15 q7 q14 q6 gnd q13 q5 q12 q4 vccq gnd q11 q3 q10 q2 vcc q9 q1 q8 q0 a0 byte a23 ce2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 notes: 1. a22 exists on 64m, 128m densities. on 32m densities this pin is a no connect (nc). 2. a23 exists on 128m densities. on 32m and 64m densities this pin is a no connect (nc). 5 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 symbol pin name a0 byte select address a1~a23 address input (32m:a0~a21, 64m:a0~a22, 128m:a0~a23) q0~q15 data inputs/outputs ce0, ce1, ce2 chip enable input we write enable input oe output enable input reset reset/deep power down mode (low enable for 56-tsop & 64-csp) reset reset/deep power down mode (high enable for 48-tsop & 48-rtsop) pin description 64 ball csp (10x13x1.2mm, 1.0mm-ball pitch) notes: 1. address a22 is only valid on 64m and 128m densities. otherwise, it is a no connect (nc). 2. address a23 is only valid on 128m densities. otherwise, it is a no connect (nc). 3. don't use (du) pins refer to pins that should not be connected. a1 a b c d e f g h 1 2345 6 78 a2 a3 a4 q8 byte a6 gnd a7 a5 q1 q0 a8 a9 a10 a11 q9 q10 vpen ce0 a12 reset q3 q11 10mm a13 a14 a15 du q4 q12 vcc a18 du du du du du a19 a20 a16 q15 du a22 ce1 a21 13 mm a17 sts oe a23 ce2 a0 du q2 vcc vccq gnd q5 q13 q6 gnd q14 q7 we nc symbol pin name sts status pin byte byte mode enable vpen erase/program/block lock enable vccq output buffer power supply vcc device power supply gnd device ground nc pin not connected internally du don't use 6 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15 a0-a23 ce0 ce1 ce2 oe we reset(*) * : reset pin for 56-tsop & 64-csp; reset pin for 48-tsop & 48-rtsop. 7 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 1. block architecture flash memory reads erases and writes in-system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. table 1. chip enable truth table ce2 ce1 ce0 device vil vil vil enabled vil vil vih disabled vil vih vil disabled vil vih vih disabled vih vil vil enabled vih vil vih enabled vih vih vil enabled vih vih vih disabled note: for single-chip applications, ce2 and ce1 can be strapped to gnd. 32 mbit 01ffff 010000 00ffff 000000 64-kword block . . . 1 1fffff 1f0000 64-kword block 31 . . . 3fffff 3f0000 64-kword block 63 64-kword block word mode (x16) 03ffff 020000 01ffff 000000 . . . 3fffff 3e0000 . . . 7fffff a[23-0]: 128mbit a[22-0]: 64mbit a[21-0]: 32mbit a[23-1]: 128mbit a[22-1]: 64mbit a[21-1]: 32mbit 7e0000 ffffff fe0000 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block byte mode (x8) 0 1 31 63 . . . 7fffff 7f0000 64-kword block . . . 128-kbyte block 127 127 0 64 mbit 128 mbit 8 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 notes: 1. see table 1 on page 7 for valid ce configurations. 2. oe and we should never be enabled simultaneously. 3. dq refers to q0-q7 if byte is low and q0-q15 if byte is high. 4. refer to dc characteristics. when vpen < vpenlk , memory contents can be read, but not altered. 5. x can be vil or vih for control and address pins, and vpenlk or vpenh for vpen . see dc characteristics for vpenlk and vpenh voltages. 6. in default mode, sts is vol when the wsm is executing internal block erase, program, or lock-bit configuration algorithms. it is voh when the wsm is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/deep power-down mode. 7. high z will be voh with an external pull-up resistor. 8. see section , "read identifier codes" for read identifier code data. 9. see section , "read query mode command" for read query data. 10.command writes involving block erase, program, or lock-bit configuration are reliably executed when vpen= vpenh and vcc is within specification. 11.refer to table 3 on page 10 for valid din during a write operation. 12.reset mode of 48-tsop & 48-rtsop types is high enabled to entering deep power down mode. table 2. bus operations command read output standby reset read id read read read write sequence array disable mode/ query status status deep (wsm off) (wsm on) power down mode notes 4,5,6 6,10,11 reset (12) vih vih vih vil vih vih vih vih vih (12) ce0,ce1,ce2(1) enabled enabled disabled x enabled enabled enabled enabled enabled oe (2) vil vih x x vil vil vil vil vih we (2) vih vih x x vih vih vih vih vil address x x x x see see x x x figure 2 table 6 vpen x x x x x x x x vpenh q (3) data out high z high z high z note 8 note 9 data out q7=data out data in q15-8=high z q6-0=high z sts high z x x high z high z high z x (default mode) (7) (7) (7) (7) 9 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 function the device includes on-chip program/erase control cir- cuitry. the write state machine (wsm) controls block erase and byte/word/page program operations. opera- tional modes are selected by the commands written to the command user interface (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. a deep powerdown mode is enabled when the reset pin of 56-tsop & 64-csp types is at gnd or reset pin of 48-tsop & 48-rtsop is at vih, minimizing power consumption. read the device has three read modes, which accesses to the memory array, the device identifier or the status register independent of the vpen voltage. the appro- priate read command are required to be written to the cui. upon initial device powerup or after exit from deep powerdown, the device automatically resets to read ar- ray mode. in the read array mode, low level input to ce0, ce1, ce2 and oe, high level input to we and reset or low level input to reset, and address signals to the address inputs (a23-a0) output the data of the addressed location to the data input/output (q15~q0). when reading information in read array mode, the de- vice defaults to asynchronous page mode. in this state, data is internally read and stored in a high-speed page buffer. a2:0 addresses data in the page buffer. the page size is 4 words or 8 bytes. asynchronous word/byte mode is supported with no additional commands required. write writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register and when vpen=vpenh block erasure pro- gram and lock-bit configuration. the cui is written when the device is enable, we is active and oe is at high level. address and data are latched on the earlier rising edge of we and ce. standard micro-processor write tim- ings are used. output disable when oe is at vih, output from the devices is disabled. data input/output are in a high-impedance(high-z) state. standby when ce0, ce1 and ce2 disable the device (see table1) and place it in standby mode. the power consumption of this device is reduced. data input/output are in a high- impedance(high-z) state. if the memory is deselected during block erase, program or lock-bit configuration, the internal control circuits remain active and the device con- sume normal active power until the operation completes. deep power-down when reset pin of 56-tsop & 64-csp types is at vil or reset pin of 48-tsop & 48-rtsop types is at vih, the device is in the deep power-down mode and its power consumption is substantially low around 5ua. during read modes, the memory is deselected and the data input/ output are in a high-impedance(high-z) state. to return from deep power down mode requires reset pin of 56- tsop & 64-csp types at vih or reset pin of 48- rtsop & 48-rtsop types at vil. after return from powerdown, the cui is reset to read array , and the status register is set to value 80h. during block erase program or lock-bit configuration modes, reset pin of 56-tsop & 64-csp types at vil or reset pin of 48-tsop & 48-rtsop types at vih will abort either operation. memory array data of the block being altered become invalid. in default mode, sts transitions low and remains low for a maximum time of tplph+tphrh until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock- bit configuration. time tphwl is required after reset goes to logic-high (vih) or reset goes to vil before another command can be written. read query the read query operation outputs block status informa- tion, cfi (common flash interface) id string, system interface information, device geometry information and mxic extended query information. 10 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 command definitions device operations are selected by writing specific address and data sequences into the cui. table 3 defines the valid register command sequences. when vpen 11 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 notes: 1. bus operations are defined in table 2. 2. x = any valid address within the device. ba = address within the block. ia = identifier code address: see figure 2 and table 14. qa = query database address. pa = address of memory location to be programmed. rcd = data to be written to the read configuration register. this data is presented to the device on a 16-1 ; all other address inputs are ignored. 3. id = data read from identifier codes. qd = data read from query database. srd = data read from status register. see table 15 for a description of the status register bits. pd = data to be programmed at location pa. data is latched on the rising edge of we. cc = configuration code. 4. the upper byte of the data bus (q8-q15) during command writes is a "don't care" in x16 operation. 5. following the read identifier codes command, read operations access manufacturer, device and block lock codes. see section 4.3 for read identifier code data. 6. if the wsm is running, only q7 is valid; q15-q8 and q6-q0 float, which places them in a high impedance state. 7. after the write to buffer command is issued check the xsr to make sure a buffer is available for writing. 8. the number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. count ranges on this device for byte mode are n = 00h to n = 1fh and for word mode are n = 0000h to n =000fh. the third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. please see figure 4. "write to buffer flowchart" for additional information. 9. the write to buffer or erase operation does not begin until a confirm command (d0h) is issued. 10.attempts to issue a block erase or program to a locked block. 11.either 40h or 10h are recognized by the wsm as the byte/word program setup. 12.program suspends can be issued after either the write-to-buffer or word-/byte-program operation is initiated. 13.the clear block lock-bits operation simultaneously clears all block lock-bits. 12 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 2. device identifier code memory map note: a0 is not used in either x8 or x16 mode when obtaining these identifier codes. data is always given on the low byte in x16 mode (upper byte contains 00h). 3fffff 3f0003 3f0002 3f0000 3effff block 63 reserved for future implementation reserved for future implementation (block 32 through 62) block 63 lock configuration 7fffff word address a[23-1]:128 mbit a[22-1]:64 mbit a[21-1]:32 mbit 7f0003 7f0002 7f0000 7effff block 127 reserved for future implementation reserved for future implementation (block 64 through 126) block 127 lock configuration 1f0003 32 mbit 1f0002 1f0000 1effff 01ffff block 31 reserved for future implementation reserved for future implementation (block 2 through 30) block 31 lock configuration 010003 010002 010000 000003 000002 000001 000000 block 1 reserved for future implementation 00ffff 000004 block 0 reserved for future implementation reserved for future implementation block 1 lock configuration block 0 lock configuration device code manufacturer code 64 mbit 128 mbit 13 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 read array command the device is in read array mode on initial device power up and after exit from deep power down, or by writing ffh to the command user interface. the read configu- ration register defaults to asynchronous read page mode. the device remains enabled for reads until another com- mand is written. the read array command functions in- dependently of the vpen voltage. read query mode command this section defines the data structure or "database" returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this informa- tion has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. query structure output the query database allows system software to gain in- formation for controlling the flash component. this sec- tion describes the device cfi-compliant interface that allows the host system to access query data. query data are always presented on the lowest-order data outputs (dq 0-7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word ad- dress for x16 devices. for a word-wide (x16) device, the first two bytes of the query structure, "q" and "r" in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-com- pliant device outputs 00h data on upper bytes. thus, the device outputs ascii "q" in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). at query addresses containing two or more bytes of in- formation, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. 14 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 word addressing byte addressing offset hex code v alue offset hex code value a15-a0 d15 - d0 a7-a0 d7 - d0 0010h 0051 "q" 20h 51 "q" 0011h 0052 "r" 21h 51 "q" 0012h 0059 "y" 22h 52 "r" 0013h p_id lo prvendor 23h 52 "r" 0014h p_id hi id# 24h 59 "y" 0015h plo prv endor 25h 59 "y" 0016h phi tbladr 26h p_id lo prvendor 0017h a_id lo altvendor 27h p_id lo id# 0018h a_id hi id# 28h p_id hi id# ... ... ... ... ... ... in all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. in addition, since the upper byte of word-wide devices is always "00h", the leading "00" has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. note: 1. the system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. therefore, word addressing, where these lower addresses are not toggled by the system, is "not applicable" for x8-configured devices. device query start location in query data with maximum query data with byte type/mode maximum device bus device bus width addressing addressing width addresses hex hex ascii hex hex ascii offset code v alue offset code v alue x16 device 10: 0051 "q" 20: 51 "q" x16 mode 10h 11: 0052 "r" 21: 00 "null" 12: 0059 "y" 22: 52 "r" x16 device 20: 51 "q" x8 mode n/a (1) n/a (1) 21: 51 "q" 22: 52 "r" table 4. summary of query structure output as a function of device and mode table 5. example of query structure output of a x16- and x8-capable device 15 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 offset sub-section name description 00h manufacturer code 01h device code (ba+2)h (2) block status register block-specific information 04-0fh reserved reserved for vendor-specific information 10h cfi query identification string reserved for vendor-specific information 1bh system interface information command set id and vendor data offset 27h device geometry definition flash device layout p (3) primary mxic-specific extended vendor-defined additional information specific to the query table primary vendor algorithm notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128 kbyte). 3. offset 15 defines "p" which points to the primary intel-specific extended query table. table 6. query structure (1) block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. offset length description address v alue (ba+2)h (1) 1 block lock status register ba+2: --00 or --01 bsr.0 block lock status 0 = unlocked ba+2: (bit 0): 0 or 1 1 = locked bsr 1-7: reserved for future use ba+2: (bit 1-7): 0 note: 1. ba = the beginning location of a block address (i.e., 008000h is block 1s (64-kb block) beginning location in word mode). table 7. block status register query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or "database". the structure sub-sections and address locations are summarized below. 16 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 offset length description add. hex v alue code 10h 3 query-unique ascii string "qry" 10 --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --31 16: --00 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 table 8. cfi identification offset length description add. hex v alue code 1bh 1 vcc logic supply minimum program/erase voltage bits 0-3 bcd 100 mv 1b: --27 2.7 v bits 4-7 bcd volts 1ch 1 vcc logic supply maximum program/erase voltage bits 0-3 bcd 100 mv 1c: --36 3.6 v bits 4-7 bcd volts 1dh 1 vpp [programming] supply minimum program/erase voltage bits 0-3 bcd 100 mv 1d: --00 0.0v bits 4-7 hex volts 1eh 1 vpp [programming] supply maximum program/erase voltage bits 0-3 bcd 100 mv 1e: --00 0.0v bits 4-7 hex volts 1fh 1 "n" such that typical single word program time-out = 2us 1f: --07 128us 20h 1 "n" such that typical max. buffer write time-out = 2us 20: --07 128us 21h 1 "n" such that typical block erase time-out = 2ms 21: --0a 1s 22h 1 "n" such that typical full chip erase time-out = 2ms 22: --00 na 23h 1 "n" such that maximum word program time-out = 2 times typical 23: --04 2ms 24h 1 "n" such that maximum buffer write time-out = 2 times typical 24: --04 2ms 25h 1 "n" such that maximum block erase time-out = 2 times typical 25: --04 16s 26h 1 "n" such that maximum chip erase time-out = 2 times typical 26: --00 na system interface information the following device information can optimize system interface software. table 9. system interface information cfi query identification string the cfi query identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). 17 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 address 32m 64m 128m 27: --16 --17 --18 28: --02 --02 --02 29: --00 --00 --00 2a: --05 --05 --05 2b: --00 --00 --00 2c: --01 --01 --01 2d: --1f --3f --7f 2e: --00 --00 --00 2f: --00 --00 --00 30: --02 --02 --02 device geometry definition this field provides critical details of the flash device geometry. offset length description code see table below 27h 1 "n" such that device size = 2 n in number of bytes 27: 28h 2 flash device interface: x8 async(28:00,29:00), 28: --02 x8/x16 x16 async(28:01,29:00), x8/x16 async(28:02,29:00) 29: --00 2ah 2 "n" such that maximum number of bytes in write buffer = 2 n 2a: --05 32 2b: --00 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or 2ch 1 more contiguous same-size erase blocks 2c: --01 1 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2dh 4 erase block region 1 information 2d: bits 0-15 = y, y+1 = number of identical-size erase blocks 2e: bits 16-31 = z, region erase block(s) size are z x 256 bytes 2f: 30: table 10. device geometry definition device geometry definition 18 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 offset(1) length description add. hex value p=31h (optional flash features and commands) code (p+0)h 3 primary extended query table 31: --50 "p" (p+1)h unique ascii string "pri" 32: --52 "r" (p+2)h 33: --49 "i" (p+3)h 1 major version number, ascii 34: --31 "1" (p+4)h 1 minor version number, ascii 35: --31 "1" (p+5)h optional feature and command support (1=yes, 0=no) 36: --0a (p+6)h bits 9-31 are reserved; undefined bits are "0". if bit 31 is 37: --00 (p+7)h "1" then another 31 bit field of optional features follows at 38: --00 (p+8)h the end of the bit-30 field. 39: --00 bit 0 chip erase supported bit 0 = 0 no 4 bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 1(1) yes(1) bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 0 no bit 6 protection bits supported bit 6 = 1 yes bit 7 page-mode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 0 no (p+9)h 1 supported functions after suspend: read array, status,query other supported operations are: 3a: --01 bits 1-7 reserved; undefined bits are "0" bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h block status register mask 3b: --01 (p+b)h 2 bits 2-15 are reserved; undefined bits are "0" 3c: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 0 no (p+c)h 1 vcc logic supply highest performance program/erase voltage bits 0-3 bcd value in 100 mv 3d: --33 3.3v bits 4-7 bcd value in volts (p+d)h 1 vpp optimum program/erase supply voltage bits 0-3 bcd value in 100 mv 3e: --00 0.0v bits 4-7 hex value in volts primary-vendor specific extended query table certain flash features and commands are optional. the primary vendor-specific extended query table specifies this and other similar information. note: 1. future devices may not support the described "legacy lock/unlock" function. thus bit 3 would have a value of "0". table 11. primary vendor-specific extended query 19 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 offset(1) length description add. hex value p=31h (optional flash features and commands) code (p+e)h 1 number of protection register fields in jedec id space. 3f: --01 01 "00h," indicates that 256 protection bytes are available protection field 1: protection description this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed (p+f)h with device-unique serial numbers. others are user-programmable. (p+10)h bits 0-15 point to the protection register lock 40: --00 00h (p+11)h byte, the section's first byte. the following bytes are factory (p+12)h pre-programmed and user-programmable. bits 0-7 = lock/bytes jedec-plane physical low address bits 8-15 = lock/bytes jedec-plane physical high address bits 16-23 = "n" such that 2 n = factory pre-programmed bytes bits 24-31 = "n" such that 2 n = user-programmable bytes note: 1. the variable p is a pointer which is defined at cfi offset 15h. table 12. protection register information offset(1) length description add. hex value p=31h (optional flash features and commands) code page mode read capability bits 0-7 = "n" such that 2 n hex value represents the number (p+13)h 1 of read-page bytes. see offset 28h for device word width to 44: --03 8 byte determine page-mode data output width. 00h indicates no read page buffer. (p+14)h 1 number of synchronous mode read configuration fields that 45: --00 0 follow. 00h indicates no burst capability. (p+15)h reserved for future use 46: note: 1. the variable p is a pointer which is defined at cfi offset 15h. table 13. page read information 20 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 * outputs c2h at protected sector address, 00h at unprotected sector address. ** only the top and the bottom sectors have protect-bit feature. sector address = (a20, a19, a18,a17,a16) = 00000b or 11111b device operation silicon id read the silicon id read mode allows the reading out of a binary code from the device and will identify its manu- facturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corre- sponding programming algorithm. this mode is func- tional over the entire temperature range of the device. to activate this mode, the two cycle "silicon id read" command is requested. (the command sequence is il- lustrated in table 14. during the "silicon id read" mode, manufacturer's code (mxic=c2h) can be read out by setting a0=vil and device identifier can be read out by setting a0=vih. to terminate the operation, it is necessary to write the read command. the "silicon id read" command func- tions independently of the vpen voltage. this command is valid only when the wsm is off or the device is sus- pended. table 14. MX28F320J3/640j3/128j3 silicon id codes and verify sector protect code type address (1) code (hex) q7 q6 q5 q4 q3 q2 q1 q0 manufacture code 00000 c2h 1 1 0 0 0 0 1 0 32m 00001 (00) 72h 0 1 1 1 0 0 1 0 device code 64m 00001 (00) 73h 0 1 1 1 0 0 1 1 128m 00001 (00) 74h 0 1 1 1 0 1 0 0 block lock configuration x0002 (2) - block is unlocked dq0=0 - block is locked dq0=1 - reserved for future use dq1-7 21 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 high z definition symbol when status notes busy? "1" "0" sr.7 no write state machine status ready busy 1 sr.6 yes erase suspend status block erase suspended block erase in progress/completed sr.5 yes erase and clear lock-bits error in block erasure or successful block 2 status clear lock-bits erase or clear lock-bits sr.4 yes program and set lock-bit error in setting lock-bit successful set block status lock bit sr.3 yes programming voltage low programming voltage programming voltage 3 status detected, operation ok aborted sr.2 yes program suspend status program suspended program in progress/ completed sr.1 yes device protect status block lock-bit detected, unlock 4 operation abort sr.0 yes reserved 5 table 15. status register definitions notes 1. check sts or sr.7 to determine block erase, program, or lock-bit configuration completion. sr.6-sr.0 are not driven while sr.7 = 0 2. if both sr.5 and sr.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se- quence was entered. 3. sr.3 does not provide a continuous programming voltage level indication. the wsm interrogates and indicates the programming voltage level only after block erase, program, set block lock-bit, or clear block lock-bits com- mand sequences. 4. sr.1 does not provide a continuous indication of block lock-bit values. the wsm interrogates the block lock-bits only after block erase, program, or lock-bit configuration command sequences. it informs the system, depend- ing on the attempted operation, if the block lock-bit is set. read the block lock configuration codes using the read identifier codes command to determine block lock-bit status. 5. sr.0 is reserved for future use and should be masked when polling the status register. high z definition symbol when status notes busy? "1" "0" xsr.7 no write buffer status write buffer available write buffer not available 1 xsr.6- yes reserved 2 xsr.0 table 16 . extended status register definitions notes: 1. after a buffer-write command, xsr.7 = 1 indicates that a write buffer is available. 2. xsr.6-xsr.0 are reserved for future use and should be masked when polling the status register. 22 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 block erase command automated block erase is initiated by writing the block erase command of 20h followed by the confirm com- mand of d0h. an address within the block to be erased is required (erase changes all block data to ffh). block preconditioning, erase, and verify are handled in- ternally by the wsm (invisible to the system). the cpu can detect block erase completion by analyzing the out- put of the sts pin or status register bit sr.7. toggle oe, ce0 , ce1 , or ce2 to update the status register. the cui remains in read status register mode until a new command is issued. also, reliable block erasure can only occur when vcc is valid and vpen = vpenh . block erase suspend command this command only has meaning while the wsm is ex- ecuting block erase operation, and therefore will only be responded to during block erase operation. after this com- mand has been executed, the wsm suspend the erase operations, and then return to read status register mode. the wsm will set the q6 bit to a "1". once the wsm has reached the suspend state, the wsm will set write to buffer command to program the device, a write to buffer command is issue first. a variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. first, the write to buffer setup command is issued along with the block address (see figure , write to buffer flowchart on page ). after the com- mand is issued, the extended status register (xsr) can be read when ce is vil. xsr.7 indicates if the write buffer is available. if the buffer is available, the number of words/bytes to be program is written to the device. next, the start ad- dress is given along with the write buffer data. subse- quent writes provide additional device addresses and data, depending on the count. after the last buffer data is given, a write confirm command must be issued. the wsm beginning copy the buffer data to the flash array. if an error occurs while writing, the device will stop writ- ing, and status register bit sr.4 will be set to a "1" to indicate a program failure. the internal wsm verify only detects errors for "1" that do not successfully program to "0" . if a program error is detected, the status register should be cleared. any time sr.4 and/or sr.5 is set, the the q7 bit to a "1". in default mode, sts will also transi- tion to voh. at this time, a read array/program command sequence can also be issued during erase suspend to read or pro- gram data in other blocks. during a program operation with block erase suspended, status register bit sr.7 will return to "0" and sts output (in default mode) will transi- tion to vol the wsm will continue to run, idling in the suspend state, regardless of the state of all input con- trol pins. the only other valid commands while block erase is sus- pended are read query, read status register, clear status register, configure, and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will auto- matically clear and sts (in default mode) will return to vol. vpen must remain at vpenh (the same vpen level used for block erase) while block erase is suspended. block erase cannot resume until program operations ini- tiated during block erase suspend have completed. read status register command the status register is read after writing the read status register command of 70h to the command user inter- face. also, after starting the internal operation the de- vice is set to the read status register mode automati- cally. the contents of status register are latched on the later falling edge of oe or the first edge of ce0, ce1, ce2 that enables the device oe must be toggle to vih or the device must be disable before further reads to update the status register latch. the read status register com- mand functions independently of the vpen voltage. clear status register command the erase status, program status, block status bits and protect status are set to "1" by the write state ma- chine and can only be reset by the clear status register command of 50h. these bits indicates various failure conditions. 23 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 device will not accept any more write to buffer com- mands. reliable buffered writes can only occur when vcc is valid and vpen = vpenh. also, successful program- ming requires that the corresponding block lock-bit be reset. byte/word program commands byte/word program is executed by a two-command se- quence. the byte/word program setup command of 40h is written to the command interface, followed by a sec- ond write specifying the address and data to be written. the wsm controls the program pulse application and verify operation. the cpu can detect the completion of the program event by analyzing the sts pin or status register bit sr.7. if a byte/word program is attempted while vpen_v penlk, status register bits sr.4 and sr.3 will be set to "1". successful byte/word programs require that the cor- responding block lock-bit be cleared. if a byte/ word pro- gram is attempted when the corresponding block lock- bit is set, sr.1 and sr.4 will be set to "1". suspend/resume command writing the suspend command of b0h during block erase operation interrupts the block erase operation and allows read out from another block of memory. writing the sus- pend command of b0h during program operation inter- rupts the program operation and allows read out from another block of memory. the block address is required when writing the suspend/resume command. the de- vice continues to output status register data when read, after the suspend command is written to it. polling the wsm status and suspend status bits will determine when the erase operation or program operation has been sus- pended. when sr.7 = 1, sr.2 should also be set to "1", indicating that the device is in the program suspend mode. sts in level ry/by mode will also transition to voh. at this time, writing of the read array command to the cui enables reading data from blocks other than that which is suspended. the only other valid commands while programming is suspended are read query, read sta- tus register, clear status register, configure, and pro- gram resume. when the resume command of d0h is written to the cui, the wsm will continue with the erase or program processes. status register bits sr.2 and sr.7 will automatically clear and sts in ry/by mode will re- turn to vol. 24 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 read configuration the device will support both asynchronous page mode and standard word/byte reads. no configuration is required. status register and identifier only support standard word/byte single read operations. table 17. read configuration register definition rm r r r r r r r 16(a16) 15 14 13 12 11 10 9 rr r r r r r r 87 6 5 4 3 2 1 notes rcr.16 = read mode (rm) read mode configuration effects reads from the flash 0 = standard word/byte reads enabled (default) array. 1 = page-mode reads enabled status register, query, and identifier reads support standard word/byte read cycles. rcr.15-1= reserved for future these bits are reserved for future use. set these enhancements (r) bits to "0". configuration command the status (sts) pin can be configured to different states using the configuration command. once the sts pin has been configured, it remains in that configuration until another configuration command is issued or rp is asserted low. initially, the sts pin defaults to ry/by operation where ry/by low indicates that the state machine is busy. ry/by high indicates that the state machine is ready for a new operation or suspended. table 19, "configuration coding definitions" on page 28 displays the possible sts configurations. to reconfigure the status (sts) pin to other modes, the configuration command is given followed by the desired configuration code. the three alternate configurations are all pulse mode for use as a system interrupt as described below. for these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 controls program complete interrupt pulse. supplying the 00h configuration code with the configuration command resets the sts pin to the default ry/by level mode. the possible configurations and their usage are described in table 19, "configuration coding definitions" on page 28. the configuration command may only be given when the device is not busy or suspended. check sr.7 for device status. an invalid configuration code will result in both status register bits sr.4 and sr.5 being set to "1". when configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns. 25 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 q7 - q2 = reserved q1 - q0 = sts pin configuration codes 00 = default, level mode ry/by (device ready) indication 01 = pulse on erase complete 10 = pulse on program complete 11 = pulse on erase or program complete configuration codes 01b, 10b, and 11b are all pulse mode such that the sts pin pulses low then high when the operation indicated by the given configuration is completed. configuration command sequences for sts pin configuration (masking bits q7- q 2 to 00h) are as follows: default ry/by level mode: b8h, 00h er int (erase interrupt): b8h, 01h pulse-on-erase complete pr int (program interrupt): b8h, 02h pulse-on-program complete er/pr int (erase or program interrupt): b8h, 03h pulse-on-erase or program complete table 18. configuration coding definitions note: 1. when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns. reserved pulse on pulse on program erase complete (1) compete (1) bits7-2 bit 1 bit 0 q7 - q2 are reserved for future use. default (q1-q 0 = 00) ry/by, level mode - used to control hold to a memory controller to prevent accessing a flash memory subsystem while any flash device's wsm is busy. configuration 01 er int, pulse mode - used to generate a system interrupt pulse when any flash device in an array has completed a block erase. helpful for reformatting blocks after file system free space reclamation or "cleanup" configuration 10 pr int, pulse mode -used to generate a system interrupt pulse when any flash device in an array has complete a program op- eration. provides highest performance for servicing continuous buffer write operations. configuration 11 er/pr int, pulse mode -used to generate system interrupts to trigger servic- ing of flash arrays when either erase or program opera- tions are completed when a common interrupt service routine is desired. 26 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 set block lock-bit commands this device provided the block lock-bits, to lock and unlock the individual block. to set the block lock-bit, the two cycle set block lock-bit command is requested. this command is invalid while the wsm is running or the device is suspended. writing the set block lock-bit com- mand of 60h followed by confirm command and an ap- propriate block address. after the command is written, the device automatically outputs status register data when read. the cpu can detect the completion of the set lock- bit event by analyzing the sts pin output or status reg- ister bit sr.7. also, reliable operations occur only when vcc and vpen are valid. with vpen _vpenlk , lock- bit contents are protected against alteration. clear block lock-bits command all set block lock-bits can clear by the clear block lock- bits command. this command is invalid while the wsm is running or the device is suspended. to clear the block lock-bits, two cycle command is requested . the device automatically outputs status register data when read. the cpu can detect completion of the clear block lock-bits event by analyzing the sts pin output or status register bit sr.7. if a clear block lock-bits operation is aborted due to v pen or v cc transitioning out of valid range, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. protection register program command the device offer a 128-bit protection register to increase the security of a system design. the 128-bits protection register are divided into two 64-bit segments. one is pro- grammed in the factory with a unique 64-bit number, which is unchangeable. the other one is left blank for customer designers to program as desired. once the customer segment is programmed, it can be locked to prevent reprogramming. reading the protection register the protection register is read in the identification read mode. the device is switched to this mode by writing the read identifier command 90h. once in this mode, read cycles from addresses retrieve the specified informa- tion. to return to read array mode, write the read array command (ffh). programming the protection register the protection register bits are programmed using the two-cycle protection program command. the 64-bit num- ber is programmed 16 bits at a time for word-wide parts and eight bits at a time for byte-wide parts. first write the protection program setup command, c0h. the next write to the device will latch in address and data and program the specified location. any attempt to address protection program commands outside the defined protection register address space will result in a status register error. attempting to program a locked protection register segment will result in a status register error. locking the protection register the user-programmable segment of the protection regis- ter is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at the intel factory to protect the unique device number. bit 1 is set using the protection program command to pro- gram "fffd" to the pr-lock location. after these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program commands to a locked section will result in a status register error. protection register lockout state is not reversible. 27 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 3. protection register memory map note: a 0 is not used in x16 mode when accessing the protection register map (see table 20 for x16 addressing). for x8 mode a 0 is used (see table 21 for x8 addressing). 88h word address 85h 4 words user programmed a[22 -1]: 64 mbit a[23 -1]: 128 mbit a[21 -1]: 32 mbit 84h 81h 80h 4 words factory programmed 1 word lock 28 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 table 20. word-wide protection register addressing word use a8 a7 a6 a5 a4 a3 a2 a1 lock both 1 0 0 0 0 0 0 0 0 factory 1 0 0 0 0 0 0 1 1 factory 1 0 0 0 0 0 1 0 2 factory 1 0 0 0 0 0 1 1 3 factory 1 0 0 0 0 1 0 0 4 user 1 0 0 0 0 1 0 1 5 user 1 0 0 0 0 1 1 0 6 user 1 0 0 0 0 1 1 1 7 user 1 0 0 0 1 0 0 0 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a23-a9 = 0. table 21. byte-wide protection register addressing word use a8 a7 a6 a5 a4 a3 a2 a1 lock both 1 0 0 0 0 0 0 0 lock both 1 0 0 0 0 0 0 0 0 factory 1 0 0 0 0 0 0 1 1 factory 1 0 0 0 0 0 0 1 2 factory 1 0 0 0 0 0 1 0 3 factory 1 0 0 0 0 0 1 0 4 factory 1 0 0 0 0 0 1 1 5 factory 1 0 0 0 0 0 1 1 6 factory 1 0 0 0 0 1 0 0 7 factory 1 0 0 0 0 1 0 0 8 user 1 0 0 0 0 1 0 1 9 user 1 0 0 0 0 1 0 1 a user 1 0 0 0 0 1 1 0 b user 1 0 0 0 0 1 1 0 c user 1 0 0 0 0 1 1 1 d user 1 0 0 0 0 1 1 1 e user 1 0 0 0 1 0 0 0 f user 1 0 0 0 1 0 0 0 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a23-a9 = 0. 29 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 4. write to buffer flowchart start set time-out write buffer data, start address x = 0 write to another block address write to buffer failed issue read status command write word or byte count to block address write e8h to block address read extended status register no no yes yes yes yes yes no no no yes xsr.7=1 ? check x=n ? abort write to buffer command? another write to buffer ? write to buffer time-out ? write next buffer data, device address x = x+1 program buffer to flash confirm d0h read status register sr.7=1? full status check if desired programming complete 30 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 5. program suspend/resume flowchart start write b0h read status register write ffh no no yes sr.7=1 ? yes sr.2=1 ? write d0h yes programming resumed write ffh read array data read array data programming completed no done reading 31 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 6. byte/word programming flowchart bus command comments operation write setup byte/ data=40h word program addr=location to be programmed write byte/word data=data to be program programmed addr=location to be programmed read status register data (note 1) standby check sr.7 1=wsm ready 0=wsm busy 1. toggling oe (low to high to low) updates the status register. this can be done in place of issuing the read status register command. repeat for subsequent pro- gramming operations. sr full status check can be done after each program operation, or after a sequence of programming opera- tions. write ffh after the last program operation to place device in read array mode. bus command comments operation standby check sr.3 1=programming to voltage error detect standby check sr.1 1=device protect detect rp=vih, block lock-bit is set only required for systems standby check sr.4 1=programming error toggling oe (low to high to low) updates the status register. this can be done in place of issuing the read status register command. repeat for subsequent pro- gramming operations. sr.4, sr.3, and sr.1 are only cleared by the clear status register command in cases where multiple lo- cation are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. start write 40h, address write data and address full status check if desired byte/word program complete read status register 0 1 sr.7= read status register data (see above) full status check procedure byte/word program successful sr.3= 0 0 0 vpp range error 1 programming error 1 device protect error 1 sr.1= sr.4= 32 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 7. block erase flowchart start write 20h to block address erase flash block(s) completed full status check if desired write confirm d0h to block address read status register no no yes suspend loop write d0h sr.7=1 ? write b0h? yes yes 33 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 8. block erase suspend/resume flowchart start block erase resumed erase completed write b0h read status register 0 0 1 write d0h sr.7= 1 sr.6= read or program? program read read array data program loop ye s no done ? read array data write ffh bus command comments operation write erase data=b0h suspend addr=x read status register data addr=x standby check sr.7 1=wsm ready 0=wsm busy standby check sr.6 1=block erase suspend 0=block erase completed write erase data=d0h resume addr=x 34 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 9. set block lock-bit flowchart start write 60h, block address set lock-bit completed full status check if desired write 01h, block address read status register no yes sr.7=1 ? read status register data (see above) full status check procedure set lock-bit successful sr.3=0 ? yes no yes voltage range error no command sequence error yes set lock-bit error no sr.4,5=1 ? sr.4=0 ? 35 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 10. clear lock-bit flowchart start write 60h set lock-bit completed full status check if desired write d0h read status register no yes sr.7=1 ? read status register data (see above) full status check procedure clear block lock-bit successful sr.3=0 ? yes no yes voltage range error no command sequence error yes clear block lock-bits error no sr.4,5=1 ? sr.5=0 ? 36 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 11. protection register programming flowchart start write c0h (protection reg. program setup) program completed full status check if desired write protect. register address/data read status register no yes sr.7=1 ? read status register data (see above) full status check procedure program successful sr.3, sr.4= yes vpen range error 1,1 1,1 protection register programming error 0,1 attempted program to locked register-aborted sr.1, sr.4= sr.1, sr.4= 37 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9, oe, and reset or reset(note 2) . . . . . . . . .-0.5 v to +12.5 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may overshoot to vcc +2.0 v for periods up to 20 ns. see figure 7. 2. minimum dc input voltage on pins a9, oe, and re- set or reset is -0.5 v. during voltage transitions, a9, oe, and reset or reset may overshoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum rat-ings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . +2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. 38 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 symbol parameter n otes typ max unit t est conditions ili input and v pen load current 1 1 ua vcc = vcc max; vccq = vccq max vin = vccq or gnd ilo output leakage current 1 10 ua vcc = vcc max; vccq = vccq max vin = vccq or gnd cmos inputs, vcc = vcc max, icc1 vcc standby current 1,2,3 25 80 ua device is disabled (see table 2) reset=vccq 0.2v or reset=vil 0.71 2 ma ttl inputs, vcc=vcc max, device is disable (see table 2), reset=vih or reset=vil icc2 vcc power-down current 2 5 ua reset=gnd 0.2v, or reset=vih iout(sts)=0ma cmos inputs, vcc=vcc max, vccq=vccq max 15 20 ma device is enabled (see table 2) icc3 vcc page mode read current 1,3 f=5mhz, iout=0ma cmos inputs, vcc=vcc max, vccq=vccq max 24 29 ma device is enabled (see table 2) f=33mhz, iout=0ma cmos inputs, vcc=vcc max, icc4 vcc word mode read current 1,3 40 50 ma vccq=vccq max device is enabled (see table 2) f=5mhz, iout=0ma icc5 vcc program or set lock-bit 1,4 35 60 ma cmos inputs, vpen=vcc current 40 70 ma ttl inputs, vpen=vcc icc6 vcc block erase or clear 1,4 35 70 ma cmos inputs, vpen=vcc block lock-bits current 40 80 ma ttl inputs, vpen=vcc icc7 vcc program suspend or block 1,5 10 ma device is disabled (see table 2) erase suspend current dc characteristics 39 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 symbol parameter n otes min max unit t est conditions vil input low voltage 4 -0.5 0.8 v vih input high voltage 4 2.0 vccq+0.5 v 0.4 v vccq=vccq2/3 min iol=2ma vol output low voltage 2,4 0.2 v vccq=vccq2/3 min iol=100ua 0.85 x v vccq=vccq min vccq ioh=-2.5ma voh output high voltage 2,4 vccq-0.2 v vccq=vccq min ioh=-100ua vpenlk vpen lockout during program, 4,6,7 2.2 v erase and lock-bit operations vpenh vpen during block erase, 6,7 2.7 3.6 v program, or lock-bit operations vlko vcc lockout voltage 8 2.2 v dc characteristics, continued notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). 2. includes sts. 3. cmos inputs are either vcc 0.2 v or gnd 0.2 v. ttl inputs are either vil or vih . 4. sampled, not 100% tested. 5. iccws and icces are specified with the device de-selected. if the device is read or written while in erase suspend mode, the device's current draw is i ccr or i ccw . 6. block erases, programming, and lock-bit configurations are inhibited when v pen ? v penlk , and not guaranteed in the range between vpenlk (max) and vpenh (min), and above vpenh (max). 7. typically, vpen is connected to vcc (2.7 v - 3.6 v). 8. block erases, programming, and lock-bit configurations are inhibited when vcc < vlko , and not guaranteed in the range between vlko (min) and vcc (min), and above vcc (max). 40 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 12. transient input/output reference waveform for vccq=3.0v-3.6v or vccq=2.7v-3.6 v test points vccq/2 output note:ac test inputs are driven at vccq for a logic "1" and 0.0v for a logic "0". input timing being, and output timing ends, at vccq/2v (50% of vccq). input rise and fall times (10% tp 90%)<5ns. vccq 0.0 input vccq/2 figure 13. transient equivalent testing load circuit note: cl includes jig capacitance test configuration c l (pf) vccq = vcc = 3.0 v-3.6 v 30 vccq = vcc = 2.7 v-3.6 v 30 device under test cl out rl=3.3k ohm 1.3v 1n914 41 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 versions vcc 3.0v-3.6v(3) 2.7v-3.6v(3) (all units in ns unless otherwise noted) vccq 3.0v-3.6v(3) 2.7v-3.6v(3) sym parameter n otes min max min max tavav read/write cycle time 32m 120 120 64m 7 120 120 128m 150 150 tavqv address to output delay 32m 120 120 64m 120 120 128m 150 150 telqv cex to output delay 32m 2 120 120 64m 2, 7 120 120 128m 2 150 150 tglqv oe to non-array output delay 2, 4 50 50 tphqv reset high to output delay 32m 180 180 64m 180 180 128m 8 210 210 telqx cex to output in low z 5 0 0 tglqx oe to output in low z 5 0 0 tehqz cex high to output in high z 5 35 35 tghqz oe high to output in high z 5 15 15 toh output hold from address, cex, or oe 5 0 0 change, whichever occurs first telfl/telfh cex low to byte high or low 5 10 10 tflqv/tfhqv byte to output delay 1000 1000 tflqz byte to output in high z 5 1000 1000 tehel cex high to cex low 5 0 0 tapa page address access time 5, 6 25 30 tglqv oe to array output delay 4 25 30 ac characteristics --read-only operations (1,2) notes:cex low is defined as the first edge of ce0 , ce1 , or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). 1. see ac input/output reference waveforms for the maximum allowable input slew rate. 2. oe may be delayed up to t elqv -t glqv after the first edge of ce0, ce1, or ce2 that enables the device (see table 2) without impact on t elqv . 3. see figures 14-16, transient input/output reference waveform for vccq = 3.0v - 3.6v or vccq = 2.7v-3.6 v, and transient equivalent testing load circuit for testing characteristics. 4. when reading the flash array a faster tglqv (r16) applies. non-array reads refer to status register reads, query reads, or device identifier reads. 5. sampled, not 100% tested. 6. for devices configured to standard word/byte read mode, r15 (tapa) will equal r2 (tavqv). 7. the performance of 64mb depends on 120ns speed grade or 150ns speed grades. 8. tphqv is reset low to output delay for 48-tsop & 48-rtsop package types. 42 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 14. ac waveform for both page-mode and standard word/byte read operations (for 56- tsop & 64-csp) note: 1. ce x low is defined as the first edge of ce0 , ce1 , or ce2 that enables the device. ce x high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). 2. for standard word/byte read operations, tapa will equal tavqv. 3. when reading the flash array a faster tglqv applies. non-array reads refer to status register reads, query reads, or device identifier reads. tavqv tavav tapa tglqx telqx tehqz tehel tghqz toh telfl/telfh tflqv/tfhqv tflqz telqv tglqv high z tphqv valid address valid address valid output valid output valid address valid address valid output valid output high z address (a23-a3) vih vil vih vil vih disable enable vil vih vil address (a2-a0) cex[e] oe [g] vih vil we [w] vih vil vcc vih vil reset[p] vih vil byte [f] voh vol data[d/q] q0- q15 43 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 15. ac waveform for both page-mode and standard word read operations (for 48-tsop & 48-rtsop) note: 1. ce x low is defined as the first edge of ce0 , ce1 , or ce2 that enables the device. ce x high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). 2. for standard word/byte read operations, tapa will equal tavqv. 3. when reading the flash array a faster tglqv applies. non-array reads refer to status register reads, query reads, or device identifier reads. 4. for 48-tsop & 48-rtsop the reset pin is high enable. tavqv tavav tapa tglqx telqx tehqz tehel tghqz toh telqv tglqv high z tphqv valid address valid address valid output valid output valid address valid address valid output valid output high z address (a23-a3) vih vil vih vil vih disable enable vil vih vil address (a2-a0) cex[e] oe [g] vih vil we [w] vih vil vcc vih vil reset[p] (note 4) voh vol data[d/q] q0- q15 44 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 ac characteristics--write operations (1,2) versions valid for all speeds unit symbol parameter n otes min max tphwl (tphel ) reset high recovery to we(cex) going low 3,10 2 us telwl (twlel ) cex (we) low to we(cex) going low 4 0 ns twp write pulse width 4 70 ns tdvwh (tdveh ) data setup to we(cex) going high 5 50 ns tavwh (taveh ) address setup to we(cex) going high 5 55 ns twheh (tehwh) cex (we) hold from we(cex) high 0 ns twhdx (tehdx) data hold from we(cex) high 0 ns twhax (tehax) address hold from we(cex) high 0 ns twph wr ite pulse width high 6 30 ns tvpwh (tvpeh) vpen setup to we(cex) going high 3 0 ns twhgl (tehgl) write recovery before read 7 35 ns twhrl (tehrl) we(cex) high to sts going low 8 500 ns tqvvl vpen hold from valid srd, sts going high 3,8,9 0 ns twhqv5 (tehqv5) set loc k-bit time 4,9 64 75/85 us twhqv6 (tehqv6) clear block loc k-bits time 4 0.5 0.70 sec twhrh1 (tehrh1) program suspend latency time to read 9 25 75/90 us twhrh (tehrh) er ase suspend latency time to read 9 26 35/40 us notes: cex low is defined as the first edge of ce0, ce1, or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). 1. read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics-read-only operations. 2. a write operation can be initiated and terminated with either ce x or we. 3. sampled, not 100% tested. 4. write pulse width (twp) is defined from cex or we going low (whichever goes low last) to cex or we going high (whichever goes high first). hence, twp = twlwh = teleh = twleh = telwh. 5. refer to table 4 for valid a in and d in for block erase, program, or lock-bit configuration. 6. write pulse width high (t wph) is defined from cex or we going high (whichever goes high first) to cex or we going low (whichever goes low first). hence, twph = twhwl = tehel = twhel = tehwl . 7. for array access, tavqv is required in addition to twhgl for any accesses after a write. 8. sts timings are based on sts configured in its ry/by default mode. 9. vpen should be held at vpenh until determination of block erase, program, or lock-bit configuration success (sr.1/3/4/5=0). 10.for 48-tsop & 48-rtsop, the reset pin is high enable. 45 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 16. ac waveform for write operations (for 56-tsop & 64-csp) notes: 1. cex low is defined as the first edge of ce0 , ce1 , or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). sts is shown in its default mode (ry/by). a. vcc power-up and standby. b. write block erase, write buffer, or program setup. c. write block erase or write buffer confirm, or valid address and data. d. automated erase delay. e. read status register or query data. f. write read array command. tvpwh (tvpeh) twhrl (tehrl) tqvvl twhqz/twhrh twph tavwh (taveh) tphwl (tphel) twp twhdx (tehdx) twheh (tehwh) twhax (tehax) telwl (twlel) tovwh (tdveh) twhgl (tehgl) din address (a) ab cd e f vih vil oe vih vil vih disable enable vil cex,(we)[e(w)] vih disable enable vil we,(cex)[w(e)] vih vil data[d/q] voh vol sts[r] vih vil vpenh vpenlk vil reset [p] vpen[v] din ain ain din valid srd 46 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 17. ac waveform for write operations (for 48-tsop & 48-rsop) notes: 1. cex low is defined as the first edge of ce0 , ce1 , or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). sts is shown in its default mode (ry/by). a. vcc power-up and standby. b. write block erase, write buffer, or program setup. c. write block erase or write buffer confirm, or valid address and data. d. automated erase delay. e. read status register or query data. f. write read array command. 2. for 48-tsop & 48-rtsop, the reset pin is high enable. twhqz/twhrh twph tavwh (taveh) tphwl (tphel) twp twhdx (tehdx) twheh (tehwh) twhax (tehax) telwl (twlel) tovwh (tdveh) twhgl (tehgl) din address (a) ab cd e f vih vil oe vih vil vih disable enable vil cex,(we)[e(w)] vih disable enable vil we,(cex)[w(e)] vih vil data[d/q] vih vil reset [p] (note 2) din ain ain din valid srd 47 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 figure 18. ac waveform for reset operation (for 56-tsop & 64-csp) note: 1. sts is shown in its default mode (ry/by). sym parameter n otes min max unit tplph reset pulse low time 2 35 us (if reset is tied to vcc , this specification is not applicable) (for 48-tsop & 48-rstop, the tplph indicates the reset pulse high time) tphrh reset high to reset during block erase, program, or 3 2 us lock-bit configuration notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if reset is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required reset pulse low time is 100ns. 3. a reset time, tphqv, is required from the latter of sts (in ry/by mode) or reset going high until outputs are valid. reset specifications (1) figure 19. ac waveform for reset operation (for 48-tsop & 48-rtsop) tphrh tplph vih vil sts (r) vih vil reset (p) note: 1. sts is shown in its default mode (ry/by). 2. for 48-tsop & 48-rtsop, the reset pin is high enable. tplph vih vil reset (p) (note 2) 48 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time. limits parameter min. typ.(2) max. units block erase time 2.0 15.0 sec write buffer byte program time 218 654 us (time to program 32 bytes/16 words) byte program time (using word/byte program command) 210 630 us block program time (using write to buffer command) 0.8 2.4 sec block erase/program cycles c1 10 cycles c2 100 c3 1,000 c4 10,000 latch-up characteristics erase and programming performance(1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c,3.3v. additionally programming typically assume checkerboard pattern. parameter symbol parameter description test set typ max unit cin input capacitance vin=0 6 8 pf cout output capacitance vout=0 8 12 pf capacitance ta=0 c to 70 c, vcc=2.7v~3.6v notes: 1. sampled, not 100% tested. 2. test conditions ta=25 c, f=1.0mhz parameter test conditions min unit minimum pattern data retention time 150 10 years 125 20 years data retention 49 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 ordering information plastic package part no. access time package type cycles (ns) mx28f128j3tbc-15c1 150/25 48-tsop 10 mx28f128j3rbc-15c1 150/25 48-rtsop 10 mx28f128j3tc-15c3 150/25 56-tsop 1,000 mx28f128j3tbc-15c3 150/25 48-tsop 1,000 mx28f128j3rbc-15c3 150/25 48-rtsop 1,000 mx28f128j3xcc-15c3 150/25 64-csp 1,000 mx28f128j3tc-15c4 150/25 56-tsop 10,000 mx28f128j3tbc-15c4 150/25 48-tsop 10,000 mx28f128j3rbc-15c4 150/25 48-rtsop 10,000 mx28f128j3xcc-15c1 150/25 64-csp 10 mx28f128j3xcc-15c4 150/25 64-csp 10,000 mx28f640j3tc-12c3 120/25 56-tsop 1,000 mx28f640j3iac-12c3 120/25 48-fccsp 1,000 mx28f640j3xcc-12c3 120/25 64-csp 1,000 mx28f640j3tc-15c4 150/25 56-tsop 10,000 mx28f640j3iac-15c4 150/25 48-fccsp 10,000 mx28f640j3xcc-15c4 150/25 64-csp 10,000 MX28F320J3tc-12c3 120/25 56-tsop 1,000 MX28F320J3iac-12c3 120/25 48-fccsp 1,000 MX28F320J3xcc-12c3 120/25 64-csp 1,000 MX28F320J3tc-12c4 120/25 56-tsop 10,000 MX28F320J3iac-12c4 120/25 48-fccsp 10,000 MX28F320J3xcc-12c4 120/25 64-csp 10,000 50 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 package information 48-ball flip chip csp 51 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 56 tsop 52 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 64 csp 53 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 48 tsop 54 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 48 tsop (reverse ) 55 p/n:pm0858 rev. 0.4, jun. 07, 2002 MX28F320J3/640j3/128j3 revision history revision no. description page date 0.1 1. to add 32m/128m information all jan/17/2002 2. to modify the csp package size from 13x10mm to 10x13mm p3 0.2 1. add 48-tsop p1 apr/04/2002 2. technology name is changed from mxvand to nbit p1 3. 48-ball csp name is added "flip chip" wording p1 4. 64-ball csp naming is changed p1,4 5. mis-tying : removing verify sector 5-1 protection code from table 14 p8,19 5-2 correct program suspend/resume flowchart p30 5-3 correct block erase suspend/resume flowchart p31 0.3 1. added 48-rtsop p1,3,47 may/28/2002 2. added deep power-down spec:5ua(max.) p1,9,11,38 3. changed standby current from 120ua(max.) to 80ua(max.) p38 4. added "cx" on part number to distinguish different program p1,3,46,47 5. changed spec of tphwl(tphel) from 1us to 2us p43 6. changed spec of tphrh from 100ns to 2us p45 7. changed speed spec of 32mb from 110ns-->120ns p1,41,47 0.4 deep power down mode is entering by reset pin at vih of p3,5,6,8,9,20, jun/07/2002 48-tsop & 48-rtsop types. 64-csp & 56-tsop is still kept p37,38,41~47 reset=vil for entering deep power down mode. removed reset command p10,11 MX28F320J3/640j3/128j3 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. |
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